An integrated circuit memory device generally includes an input circuit terminal to which external signal are applied, and an output circuit terminal for providing external output signals. When an external electrostatic capacitance provides excessive static electricity inside the memory device through the input/output circuit terminals, a supply voltage terminal, or a ground terminal, internal circuits may be damaged. In particular, MOS transistors inside the memory device typically include oxide insulating layers that may be easily damaged. Electrostatic damage to these insulating layers may result in poor performance for the MOS transistor. Various models have been developed for electrostatic discharges (ESD) wherein different models approximate the different capacitances which may produce static electricity. One such model is a charged device model (CDM) wherein charges of a strongly charged memory device are rapidly discharged through unspecified input/output pins. Such a discharge may destroy insulating layers within the device.
To provide rapid data output in a memory device, the voltage of a supply voltage line and a ground voltage line may change quickly and severely as a result of the flow of instantaneous current through data output circuits. These voltage changes may affect other periphery circuits thereby generating noise at the output terminal. The supply voltage and ground voltages lines at the output terminal of a data output circuit are thus electrically separated from the output terminals of other periphery circuits. It is thus possible to reduce the transmission of noise signals generated at the output terminal of the data output circuit to the periphery circuits along the supply voltage and ground voltage lines. This technique is discussed, for example, in Japanese Patent No. 62-169464.
FIG. 1 is a circuit diagram of a data output circuit connected to two or more divided ground lines according to the prior art. As shown in FIG. 1, the data output circuit includes an inverter of a periphery circuit wherein an input signal DOD1b is applied to an input terminal; a PMOS transistor 3 and an NMOS transistor 5 are serially connected between a supply voltage terminal Vcc and a ground voltage line VSS1P. The data output circuit also includes an output driver wherein an input signal DOU1b is applied to an input terminal; and a PMOS transistor 7 and an NMOS transistor 9 serially connected between a supply voltage terminal Vcc and a ground voltage line VSS1IO. The data output circuit further includes an impedance component Z1 connected between the ground voltage line VSS1P and the ground voltage line VSS1IO. A node DOD1 connects the output terminal of the inverter to the gate of the NMOS transistor 9.
As discussed above, the impedance component Z1 is electrically connected between the ground voltage lines VSS1IO and VSS1P. The impedance value of the impedance component Z1 should thus be maintained at as high an impedance as possible to reduce the generation and transmission of noise. In this circuit, however, electrostatic discharge according to the charged device model may cause dielectric breakdown as a negative voltage or a ground voltage is applied to an external pin I/O1 when the integrated circuit memory device is strongly charged. This electrostatic discharge may cause the NMOS transistor 9 to operate as an NPN bipolar transistor when a negative voltage or a ground voltage is applied to the output pin I/O1 because the two ground voltage lines VSS1IO and VSS1P may be strongly charged. In other words, the source, drain, and bulk substrate of the NMOS transistor 9 may serve as the collector, emitter, and base of the NPN bipolar transistor. The NMOS transistor 9 may thus become a common emitter circuit allowing current to flow from the ground voltage line VSS1IO to the output pin I/O1.
The NMOS transistor 5 may also operate as an NPN bipolar transistor thus allowing current to flow from the ground voltage line VSS1P to the node DOD1. As this current cannot flow through the gate of the transistor 9 to the output pin I/O1, the potential of the node DOD1 may increase to the same level as that of the ground voltage line VSS1P. Accordingly, a relatively high potential difference may be generated between the node DOD1 and the output pin I/O1. This potential difference may be maintained for a relatively long period of time because the current may not flow rapidly from the ground voltage line VSS1P and the node DOD1 to the ground voltage line VSS1IO through the output pin I101. This potential difference may thus generate ESD stress thereby damaging or destroying the gate insulator of the NMOS transistor 9 between the node DOD1 and the output pin I/O1. One approach to reducing the ESD stress problem is to reduce the impedance component which is provided between the two ground voltage lines VSS1IO and VSS1P.
FIG. 2 is a circuit diagram of a second data output circuit according to the prior art. As shown, this data output circuit includes a signal delay circuit including a resistor R and a capacitor C connected to the node DOD2 to reduce the potential difference across the gate dielectric layer of the NMOS transistor 9. The resistor and capacitor thus provide an RC circuit producing a signal delay. With this circuit configuration, however, the potential difference between the node DOD2 and the output pin I/O2 may be reduced, but ESD stress may still occur when the device is more strongly charged. Furthermore, the signal transmission capability of the node DOD2 is lowered as a result of the RC delay of the signal delay circuit thus reducing the performance of the output driver.
FIG. 3 is a circuit diagram of third data output circuit according to the prior art. In this circuit, the impedance between the two ground voltage lines VSS1IO and VSS1P is reduced by providing an electrical connection therebetween. In other words, the two ground voltage lines are combined into one line. Accordingly, current may flow rapidly from the two ground voltage lines VSS3IO and VSS3P to the output pin I/O3 because the NMOS transistor 9 operates as a NPN bipolar transistor as discussed above and because the two ground voltage lines are directly connected to each other. It is thus possible to reduce the instantaneous generation of high potential differences. A noise signal generated at the output driver, however, may be directly applied to the output terminal of the periphery circuit so that noise signals reduce the performance of the device.